1. Field of the Invention
The present invention relates in general to a semiconductor memory device, and more particularly to a non-overlap signal generation circuit for generating non-overlapped signals at a buffer stage of a high-speed memory device.
2. Description of the Prior Art
Generally, a semiconductor memory device comprises data and address input buffers, each of which outputs two signals of complementary logic levels with respect to one input signal. Because the logic levels of the output signals are complementary to each other, they must be non-overlapped. To this end, a non-overlap signal generation circuit has widely been used.
Referring to FIG. 1, there is shown a circuit diagram of a conventional non-overlap signal generation circuit for the semiconductor memory device. As shown in this drawing, the conventional non-overlap signal generation circuit comprises two inverters I1 and I2 connected in series for inverting sequentially an input signal, and a non-overlap circuit 10 for generating two non-overlapped output signals A and /A of complementary logic levels with respect to the input signal. The non-overlap circuit 10 includes an inverter I3 and a NAND gate ND1 connected in series to an output terminal of the inverter I2 for inputting an output signal from the inverter I2 and generating the first output signal A, and a NAND gate ND2 for inputting the output signal from the inverter I2 and generating the second output signal /A.
The input signal is sequentially inverted by the inverters I1 and I2. Then, the output signal from the inverter I2 is passed through a first path consisting of the inverter I3 and the NAND gate ND1 and then outputted as the first output signal A. Also, the output signal from the inverter I2 is passed through a second path consisting of the NAND gate ND2 and then outputted as the second output signal /A. The NAND gate ND1 has one input terminal connected to an output terminal of the NAND gate ND2, one input terminal of which is cormected to the output terminal of the NAND gate ND1.
The operation of the conventional non-overlap signal generation circuit for the semiconductor memory device will hereinafter be described in detail with reference to FIGS. 2 and 3. FIG. 2 is a detailed circuit diagram of the non-overlap circuit 10 in FIG. 1 and FIG. 3 is a timing diagram illustrating an operation of the non-overlap circuit 10 in FIG. 2.
In FIG. 2, the inverter 13 includes a PMOS transistor 101 and an NMOS transistor 111. The NAND gate NDI includes PMOS transistors 102 and 103, and NMOS transistors 112 and 113. The NAND gate ND2 includes PMOS transistors 104 and 105, and NMOS transistors 114 and 115.
The input signal is sequentially inverted by the inverters I1 and I2 and then applied to the inverter I3, which has a low threshold voltage. First, in the case where the input signal is transited from logic "0" to logic "1", the PMOS transistor 101 is turned off, whereas the NMOS transistor 111 is turned on. As a result, the output of the inverter I3 becomes logic "0". Then, in the NAND gate ND1, the PMOS transistor 102 is turned on, whereas the NMOS transistor 112 is turned off. As a result, the output of the NAND gate ND1 is charged, thereby causing the first output signal A to become logic "1".
In the NAND gate ND2, in response to the input signal of logic "1", the PMOS transistor 104 is turned off, whereas the NMOS transistor 114 is turned on. Each of the PMOS transistor 105 and the NMOS transistor 115 has a gate for inputting the first output signal A from the NAND gate ND1. In response to the first output signal A from the NAND gate ND1, the PMOS transistor 105 is turned off, whereas the NMOS transistor 115 is turned on. As a result, the output of the NAND gate ND2 is discharged, thereby causing the second output signal /A to become logic "0". At this time, because the turning-on of the NMOS transistor 115 is somewhat delayed, the output of the NAND gate ND2 is discharged slower than the charging operation of the output of the NAND gate ND1.
In result, in the case where the input signal is transited from logic "0" to logic "1", the logic "1" charging time of the first output signal A is shorter than the logic "0" discharging time of the second output signal /A, so that the first and second output signals A and /A carmot be overlapped.
The above operation may be applied in a similar mamer with respect to the case where the input signal is transited from logic "1" to logic "0".
In other words, the conventional non-overlap signal generation circuit is adapted to obtain the non-overlapped signals using a difference between the logic "1" charging time and the logic "0" discharging time.
However, the above-mentioned conventional non-overlap signal generation circuit has a disadvantage in that a sufficient non-overlap interval cannot in practice be obtained because of a time delay when the output of one NAND gate is applied to the input of the other NAND gate. In order to make up for this problem, a delay circuit may be employed. In this case, however, a chip area is increased and a transfer time between the input and output of the signal is increased. These have a bad effect on a high-speed operation of the semiconductor memory device.